Implantable stimulation devices generate and deliver electrical stimuli to nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder sublaxation, etc. The description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227. However, the present invention may find applicability in any implantable stimulator.
As shown in FIGS. 1A and 1B, a SCS system typically includes an Implantable Pulse Generator (IPG) 100, which includes a biocompatible device case 30 formed of a conductive material such as titanium for example. The case 30 typically holds the circuitry and a battery for powering the IPG, although IPGs can also be powered via external RF energy and without a battery. The IPG 100 includes at least one electrode array 102 containing several electrodes 106. The electrodes 106 are carried on a flexible body 108, which also houses the individual electrode leads 112 coupled to each electrode. In the illustrated embodiment, there are eight electrodes on array 102, labeled E1-E8, although the number of arrays and electrodes is application specific and therefore can vary. The array 102 couples to the IPG 100 using a lead connector 38, which is fixed in a non-conductive header material 36, and which can comprise an epoxy for example. A communication coil 13 allows for telemetry of data to and from the IPG 100 from a device external to the patient, as is well known. An additional coil may be present to allow the battery to be recharged from an external device, as is also well known.
FIGS. 2A-2C illustrate typical pulses used in an IPG such as IPG 100, and the circuitry used to construct the pulses. Shown in FIG. 2A is a bi-phasic current pulse that issues a constant current of a given amplitude (amp) and pulse width (pw) between electrodes E1 and E2. Each pulse comprises a plurality of pulse phases, and is repeated in a period at a frequency f. The amplitude, pulse width, and frequency of the pulses can be patient-dependent, and may be arrived at by experimentation—i.e., based on what provides good therapy for the patient.
Circuitry for creating the pulses is shown in FIG. 2B and comprises timing channel circuitry 150 and stimulation circuitry 160 coupled via a digital bus 155. Stimulation circuitry 160 comprises a current source (PDAC) 83, a current sink (NDAC) 84, a switching matrix 85, and passive recovery switches 86, each of which will be explained subsequently. The PDAC 83 and NDAC 83 are so named because the amplitude of the analog current they source or sink is digitally controllable (hence, they are Digital-to-Analog Converters, or DACs), and because they are typically made from P-channel and N-channel transistors respectively.
Therapeutically meaningful phases of the example pulses in FIG. 2A will be explained first, starting with phase 1. In phase 1, electrode E1 acts as the cathode or sink for the current pulse, while electrode E2 acts of the anode or source of the current pulse. Thus, sourced current of the desired amplitude is issued from the PDAC 83 to E2 by closing an appropriate switch in the switching matrix 85, while sunk current of that same amplitude is drawn into the NDAC 84 from E1 by closing an appropriate switch in the switching matrix 85. This causes the current to flow from E2 to E1 through the patient's tissue (R). Notice that the pulses at E1 and E2 during phase 1 have the same amplitude (although of opposite polarities) and the same pulse width (pw), so that an excess of charge does not build up in the patient's tissue, R.
Because the pulse is bi-phasic, phase 1 is eventually followed by a second phase (phase 2), which in this example comprises a reversal of the polarity of the pulses at the two electrodes. Thus, in phase 2, E1 now acts as the anode, and E2 as the cathode, such that current now flows through the tissue R in the opposite direction. Phase 2, as is known, is useful to recover any excess charge that might have formed on any capacitances in the current path, such as the decoupling capacitors C1 and C2 coupled to electrodes E1 and E2 respectively (FIG. 2B). Connecting decoupling capacitors C1-CN to the electrodes E1-EN acts as a safety measure to prevent direct DC current injection into the patient. However, the storage of charge across such capacitors during the provision of the current is generally undesired. Reversing the current through those capacitances during phase 2 seeks to actively recover such stored charge, and thus phase 2 is sometimes referred to as an “active recovery” phase. To actively recover stored change in this fashion, it is preferable that the same amount of charge be passed in phase 2 as was passed in phase 1, which is most easily (and symmetrically) done by making the amplitude and pulse width of phase 2 equal to phase 1. However, one skilled will realize that symmetry between the pulses in phase 1 and phase 2 is not strictly necessary. For example, a pulse of lower amplitude and longer pulse width in phase 2 can also equate to the same amount of charge passed during phase 1. The polarity reversal of the pulses in phase 2 can be accomplished by the switching matrix 85, which in phase 2 will couple E1 to the PDAC 83, and E2 to the NDAC 84.
To ensure complete recovery of any stored charge, the active recovery phase (phase 2) can be followed by a passive recovery phase, as shown in FIG. 2A. In this passive recovery phase, the decoupling capacitors C1-C2 connected to previously-active electrodes E1 and E2 are shorted to a common potential via passive recovery switches 86 (FIG. 2B). In the example illustrated, this common potential, Vbat, comprises the voltage of the battery within the IPG 100, although other reference potentials could be used as well. Shorting the capacitors to Vbat effectively shorts them through the patient's tissue, and thus equilibrates any stored charge to assist in charge recovery. Some architectures may short only the previously-active electrodes by closing only the passive recovery switches 86 coupled to those electrodes, while other architectures will short all of the electrodes by closing all of the passive recovery switches 86.
Other pulse phases in each period are shown in FIG. 2A. Preceding pulse 1 is a pre-pulse phase, which is of low amplitude and long duration, and of opposite polarity to the phase 1 pulse that follows it. Experimentation suggests that the use of such a pre-pulse can help to assist in recruiting deeper nerves in an SCS application, although use of such a pre-pulse is not strictly necessary. An interpulse period between phases 1 and 2 of short duration allows the nerves to stabilize after being stimulated in phase 1. A quite phase follows the passive recovery phase, and essentially acts as a waiting phase before the next period of pulses issues. The duration of the quite phase will depend on the durations of the phases that precede it in the period, as well as the frequency (f) at which the periods issue. There may be other pulses phases for different purposes; the phases shown in FIG. 2A are merely typical.
Referring again to FIG. 2B, the various phases of each period are controlled by timing channel circuitry 150, which digitally controls the various elements in the stimulation circuitry 160 via digital bus 155. There can be several timing channels circuitries 150 operating in a given IPG 100, defining other pulse sequences perhaps issued concurrently on other electrodes. However, only one timing channel circuitry 150 is illustrated for simplicity. The timing channel circuitry 150 receives and stores the data necessary to define the various phases in each pulse period. Such pulse parameters are provided to the timing channel circuitry 150 from control circuitry (e.g., a microcontroller) 110 via a digital bus 115. The control circuitry 110 in turn typically receives the pulse parameters wirelessly from an external device, such as an external controller. An external controller is typically a hand-held device usable by a patient or her clinician to select the pulse parameters, such as amplitude, pulse width, frequency, the electrodes to be used, and whether they are to act as anodes or cathodes.
FIG. 2C shows further details of the timing channel circuitry 150. Shown are a timer 170 and a register bank 180. The timer 170 stores the durations (pulse widths) of the phases in the period, while the register bank 180 stores control information, amplitude, active electrode, and electrode polarity information for the phases. Thus, a first register in the timer 170 stores the pulse width of the first pulse phase in the period (the pre-pulse (pwpp) in the example of FIG. 2A), and the corresponding first register in the register bank 180 stores its control information (cntlpp) amplitude (amppp), active electrode, and electrode polarities. A second register in the timer 170 stores the pulse width of the next pulse phase (phase 1 (pwp1)), and the corresponding second register in the register bank 180 stores the control information (cntlp1), amplitude (ampp1), active electrode, and electrode polarity for phase 1. Data for subsequent pulse phases (interphase (ip), phase 2 (p2), passive recovery (pr), and quite (q)) are similarly stored in the timer 170 and register bank 180. The timer 170 may comprise a state machine in one example.
The control data in the registers (cntlx) contains information necessary for proper control of the stimulation circuitry 160 for each phase. For example, during the passive recovery phase, the control data (cntlpr) would instruct certain passive recovery switches 86 to close, and would disable the PDAC 83 and the NDAC 84. By contrast, during active phases, the control data would instruct the passive recovery switches 86 to open, and would enable the PDAC 83 and the NDAC 84.
Each register in the register bank 180 is, in one example, 96 bits in length, with the control data for the phase in the first 16 bits, the amplitude of the phase specified in the next 16 bits, followed by eight bits for each electrode. Each of the eight electrode bits in turn specifies the polarity (P) of the electrode in a single bit, with the remaining 7 bits specifying the percentage (%) of the amplitude that that electrode will receive. Thus, for the pre-pulse phase, the polarity bit P for E1 would be a ‘1’, specifying that that electrode is to act as an anode, and thus will receive sourced current of the specified amplitude (amppp) from PDAC 83. The remaining seven bits for E1 would digitally represent 100%, indicating that E1 is to receive the entirety of the sourced current during the pre-pulse phase. (In more complicated examples, the sourced or sunk currents could be shared between electrodes, and thus smaller percentages would be indicated in the trailing seven bits for those electrodes). The polarity bit P for E2 during the pre-pulse phase would be a ‘0’, specifying that that electrode is to act as a cathode, and thus will sink current as controlled by NDAC 84. Again, the remaining seven bits for E2 would digitally represent 100%, indicating that E2 is to receive the entirety of the sunk current during the pre-pulse phase.
The other registers in register bank 180 are programmed similarly for each phase. For example, all of the bits for E3-E8 in all of the registers would be set to zero for the example pulse phases of FIG. 2A, because those electrodes are not implicated. The amplitudes for the interphase (ampip), passive recovery (amppr), and quite (ampq) phases would be set to zero as those phases do not require the PDAC 83 or NDAC 84 to actively issue any current.
The goal of the timing channel circuitry 150 is to send data from an appropriate register in the register bank 180 to the stimulation circuitry 160 at an appropriate point in time, and this occurs by control of the timer 170. As noted earlier, the pulse widths of the various phases are stored in the timer 170. Also stored at the timer is the frequency, f, the inverse of which (1/f) comprises the duration of each period. Knowing this period, the timer 170 can cycle through the durations of each of the pulse widths, and send the data in the register bank 180 to the stimulation circuitry 160 at the appropriate time. Thus, at the start of the period, the timer 170 enables a multiplexer 190 to pass the values stored in the first register for the pre-pulse to bus 155, which enables stimulation circuitry 160 to establish the pre-pulses at electrodes E1 and E2. After time pwpp has passed, the timer 170 now enables the multiplexer 190 to pass the values stored in the second register for phase 1 to the stimulation circuitry 160 to establish the phase 1 pulses at the electrodes. The other registers are similarly controlled by the timer 170 to send their data at appropriate times. This process of cycling through the various pulse phases continues, and eventually at the end of quite phase, i.e., at the end of pwq, the timer 170 once again enables the pre-pulse data, and a new period of pulses is established.
This approach for controlling the stimulation circuitry 160 in accordance with each phase of the pulse period is adequate, but the inventors have found that this approach also suffers from certain shortcomings. A significant shortcoming is the lack of flexibility that the timing channel circuitry 150 provides to define more complex pulses. Take the pulse illustrated in FIG. 3 for example. This pulse generally contains the same phases as illustrated in FIG. 2A, but the currents specified during the therapeutically-meaningful phases (phases 1 and 2) are not constant currents, but instead comprise ramped currents. Experimentation suggests that such ramped pulses can be therapeutically useful in certain situations. Yet, the timing channel circuitry 150 as illustrated in FIG. 2C cannot direct the stimulation circuitry 160 to produce ramped pulses of this type, because only a constant amplitude can be specified for each phase in the register bank 180.
The inventors recognize that one could approximate a ramped pulse using the architecture of FIG. 2C by breaking the ramped pulse phases into a plurality of shorter phases, each with a constant current defining the ramp in a stair-wise fashion, as shown superimposed on phases 1 and 2 for electrode E1 in FIG. 3. However, this would require expanding the register bank 180 to accompany the increased number of phases in the period. Assume for example that to form a suitably-smooth ramp it would be necessary to parse both of phases 1 and 2 into ten smaller phases. The period would then comprise 24 different phases: the 20 phases needed in each of phases 1 and 2, the pre-pulse phase, the inter-pulse phase, the passive recovery phase, and the quiet phase. Because the register bank 180 must contain a register for each phase in the period, that bank 180 would then need 24 different registers. The 96 bits needed for each register in the bank 180 typically comprise flip flops, and so in this example 2304 (96*24) flip flops would be required, or more if the IPG 100 supports further numbers of electrodes. If the design of the integrated circuit is already fixed, and contains less than 24 registers, then the stair-wise approximation of the ramped pulses posited above simply could not be realized in that design. In short, the integrated circuit designer must either provide an undue number of area-intensive registers in register bank 180 to potentially handle the design of complex pulses in the future, or provide a limited number of such registers and forego the use of such complex pulses; neither option is desirable.
Furthermore, flip flops require significant layout area on the integrated circuitry in which the stimulation circuitry 160 is typically formed, which is undesirable. Further, the flip flops consume power when they are clocked, which can lead to complexity in gating the clocks to save power. The problem of excessive layout space is compounded by the fact that there may be more than one timing channel circuitry 150 operating in the device, as mentioned earlier. If the design of the integrated circuit is already fixed, and contains less than 24 registers, then the stair-wise approximation of the ramped pulses posited above simply could not be realized in that design. In short, the integrated circuit designer must either provide an undue number of area-intensive registers in register bank 180 to potentially handle the design of complex pulses in the future, or provide a limited number of such registers and forego the use of such complex pulses; neither option is desirable.
The multiplexer 190 also takes considerable layout and control. The multiplexer 190 must generally receive all 96 bits from each register, and so there are a total of 576 (96*6) bits being input to the multiplexer 190 in the example of FIG. 2C. The multiplexer 190 must in turn drive all of the 96 selected bits to the stimulation circuitry 160, which places power constraints on the system. Again, if there is more than one timing channel circuitry 150, such complexities and power issues are multiplied.
Also regrettable in the inventor's opinion is the fact that, depending on the particular phases in the pulse, certain of the register values in the register bank 180 will necessarily be irrelevant. For example, the amplitude and electrode values will necessarily be zero (or don't care values) for the illustrated interpulse, passive recovery, and quite phases. If the functions of the various phases are known in advance, the number of flip flops needed in the register bank (and thus the total number of inputs to the multiplexer 190) could be reduced. For example, if it is known in advance that the third register will always hold data for the interphase, the fifth register will always hold data for passive recovery, and the sixth register will always hold data for the quite phase, then those registers need not contain flip flops for holding the amplitude and electrode values. But reducing the number of flip flops in a given register limits future flexibility of the device. For example, if the registers just discussed above were made smaller, then those registers could not be used in the future for active stimulation phases.
A better solution is therefore needed to the aforementioned problems, and is provided by this disclosure.